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position-1

 

SRAM Embedded Memory Designer

Position can be located in San Diego, CA or Santa Clara, CA

Develop memory architectures and circuit implementation techniques. Schematic entry, simulation of major blocks, layout planning, layout supervision and interface with CAD team for full verification and model generation.

– Direct industry experience of at least 5 years or more designing embedded memories for SoC applications

– Deep understanding of SRAM/Register File architectures and advanced custom circuit implementations

– Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation

– Experience with physical implementation (layout) and layout supervision. Direct experience and familiarity with tight pitch-matched memory layout designs

– Extensive knowledge of physical implementation impact on circuit performance

– Direct experience with the most advanced technology nodes. Familiarity with variation-aware design in nanometer technology nodes

Required: Bachelor’s, Electrical Engineering

Preferred: Master’s, Electrical Engineering

position-2

One-Time-Programmable/Non

Volatile Memory Circuit Design Engineer
 
Position can be located in San Diego, CA or Santa Clara, CA

– Transistor-level digital circuit design.

 
– Memory or Non-volatile Memory Circuit design.
 
– Characterization and generation of timing files for Memory or Non-Volatile Memory circuits.
 
– Design validation and timing verification of Memory or Non-Volatile Memory circuits.
 
– Post Layout Extraction & Simulation, testing in conjunction with silicon validation.
 
– Working with Layout designers.
– At least 2 years of industry experience as a memory or non-volatile memory circuit designer.
 
– Experience in any type of RAM/ROM memory or non-volatile memory circuit design is highly valued.
 
– Low-Power Digital Circuit Design experience in CMOS.
 
– Good understanding of basic CMOS device physics is a plus.
– Transistor-level circuit design/analysis knowledge is required.
 
– Experience in running circuit simulation tools (FINESIM, HSIM, HSPICE etc.) is required.
– Experience in writing Spice stimulus and measurement files is required.
– Must have prior experience with Cadence circuit design tools (Schematic, Analog Artist, and Layout).
 
– Experience with statistical design methodology (generating and analyzing Monte-Carlo results) is a plus.
– Familiarity with generating views for ASIC design such as CPF, UPF, Apache views for IR drop analysis and LPE extraction is a plus.

Required: Bachelor’s, Electrical Engineering

Preferred: Master’s, Electrical Engineering

If you’re interested, contact kerker0312_ATNOSPAM_gmail.com (_ATNOSPAM_=@) with your resume.

Any level experience is ok to send resume.

新创基金会免责声明

本启事已在2013年6月14日中国科大手机报发布。